1. Field of the Invention
The present invention generally relates to the field of semiconductor memories, and particularly to electrically programmable non-volatile memories such as, for example, EPROMs, EEPROMs and Flash memories. Specifically, the invention concerns a method and device for programming an electrically programmable non-volatile memory.
2. Description of the Related Art
Non-volatile, electrically programmable semiconductor memories have memory cells formed by MOS transistors, whose threshold voltage can be varied electrically to store the desired information.
The number of different values that the threshold voltage of a memory cell may take depends on the number of bits that the memory cell is intended to store. For example, in two-level memories having memory cells intended to store only one bit each, the threshold voltage of each memory cell can take one of two different values, which are associated with the two opposite binary logic states (“1” and “0”). In multi-level memories, whose memory cells are intended to store more than one bit, the number of different threshold voltage values is equal to 2n, where n identifies the number of bits stored in each memory cell. Multi-level memories are also known in which n bits are stored in k memory cells, where k<n and n/k is a non-integer number; in this case, the number of different values that the memory cell threshold voltage may take is higher than two, but not equal to a power of two.
Programming a memory cell means setting the memory cell threshold voltage to the desired value, starting from a memory cell erased condition in which the threshold voltage value is equal to or lower than the lowest of the prescribed values. Typically, in order to increase the memory cell threshold voltage, electrons are injected into a memory cell floating gate of, e.g., polysilicon, or into a memory cell charge trapping element (typically, a layer of silicon nitride); the charge present in the floating gate or charge trapping element affects the formation of a conductive channel when a gate voltage is applied to a memory cell control gate.
Electrons are for example injected into the floating gate or charge trapping element by means of the channel hot-electron injection mechanism, which is triggered by applying suitable programming voltages to the memory cell terminals.
The data stored in the memory cell are retrieved by accessing the memory cell in read conditions. Prescribed read voltages are applied to the memory cell terminals, and the current sunk by the memory cell is sensed. The higher the memory cell threshold voltage, the lower the current sunk by the memory cell. The data stored in the memory cell are thus determined by comparing the sensed current to a prescribed reference current (a plurality of reference currents in the case of a multi-level memory).
Conventional programming algorithms call for applying to the memory cell a sequence of programming pulses, each programming pulse providing for applying to the memory cell terminals the proper programming voltages for a prescribed, relatively short time. Each programming pulse determines a slight increase in the memory cell threshold voltage. After each programming pulse, the memory cell threshold voltage is checked (verified) to assess whether the memory cell has been programmed (program verify phase). In order to verify the threshold voltage value, the memory cell is accessed in reading. Typically, in the program verify phase the conditions in which the programming state of the memory cell is ascertained are deliberately made more critical compared to the standard memory cell read access. This means that a memory cell that would be detected as programmed in the standard read conditions may be detected as non-programmed in the program verify conditions, if the memory cell threshold voltage is not adequately high. This assures that the memory cell is programmed with a prescribed margin. Unfortunately, the actual conditions in which a programmed memory cell is normally read may depart from the program verify conditions to such an extent that the programmed memory cell may be read as non-programmed even if it passed the program verify test during the programming phase.
Therefore a need exists to overcome the problems discussed above.